1. Field of the Invention
The invention relates to semiconductor fabrication, and in particular relates to a metal oxide semiconductor transistor (MOS transistor) having a trench gate and a method of fabricating the same.
2. Description of the Related Art
Semiconductor devices such as MOS transistors continue to develop achieving high performance, high integration and high operating speed. With continued integration the size of MOS transistors on a semiconductor substrate must to be reduced. For example, higher integration of MOS transistors can be achieved by reducing gate length and/or source/drain region size. However, this may result in the short channel effect and significantly affect the performance of a semiconductor device such as a MOS transistor. U.S. Pat. No. 6,150,693 to Wollesen discloses a MOS transistor having a V-shaped trench and a gate oxide layer formed on the sidewall of the V-shaped trench. The gate fills the V-shaped trench. US patent publication number 2005/0001252 A1 to Kim et al. discloses a semiconductor device, a MOS transistor having a trench gate to alleviate the problem of the short channel effect.
Channel length of a semiconductor device having a trench gate is generally determined by the etch depth of the trench for a gate and the ion implantation depth of the source/drain region. The trench for a gate is conventionally formed by one-step etching of the semiconductor substrate. This may result in a large trench depth difference between the center and the edge of a semiconductor wafer, thus, the channel lengths of the MOS transistors in the center and edge of the semiconductor wafer are not uniform. That is to say, in a conventional method, process uniformity is not easily controlled and there is a problem of channel length variation in the prior arts.